Recently, a PN-type voltage controlled oscillator (VCO) is widely used because of the low power consumption. However, when the PN-type VCO is applied in a low-voltage application, for example a supply voltage is 1.15V, transistors within the PN-type VCO may operate in a triode region, thereby the power consumption may be increased or the VCO may fail to obtain a stable oscillation. For example, when the PN-type VCO is in a worst corner, a threshold voltage (Vth) of NMOS and PMOS within the PN-type VCO may be up to 0.6V that is greater than a common voltage of the PN-type voltage controlled oscillator (e.g. 1.15V/2=0.575V), causing the NMOS and PMOS operate in the barely-on region. To solve this worst corner problem, one solution is to increase sizes of the NMOS and PMOS to increase the transconductance, however, the larger size NMOS and PMOS within the PN-type VCO may cause a larger power consumption when the PN-type VCO is in a better corner (the threshold voltage (Vth) may be 0.3V-04V).
Therefore, how to design a VCO to always function well with lower power consumption no matter in the worst corner or the better corner is an important topic.